A low voltage differential signaling (LVDS) receiver, being compliant with Institute of Electrical and Electronics Engineers (IEEE) and Telecommunications Industry Association/Electronic Industries Alliance (TIA/EIA) standards, is typically capable of receiving a minimum of 100 millivolts (mV) peak to peak voltage swing with a common mode voltage ranging from as low as 50 mV to as high as 2350 mV, while operating on a 2.5V/3.3V supply voltage with a standard variation of about +/−10%. This receiver draws its input voltage across a 100-ohm resistor coupled across its two terminals (e.g. a differential signal with one inverted and one non-inverted input), and coupled to the driver, at a far end, through transmission lines.
The cost of manufacturing such receiver can be reduced e.g. by using thin oxide transistors to design high supply operated circuits. Although the use of thin oxide transistors can reduce the fabrication cost, the risk of oxide breakdown is increased at such high voltages as the thin oxide transistors in the latest technologies are only capable of handling a maximum voltage of around 2.0V between any two terminals of the respective transistors. As a result, the use of such transistors in a high-voltage system demands extra design measures just to ensure that there are no voltages between any two terminals of the respective transistors used in the circuit that are higher than the acceptable limits of the technology. However, the fabrication cost optimization may outweigh the extra circuit cost if the designer can avoid the problem of oxide breakdown.
Moreover, as the input voltage range of an LVDS receiver is up to 2.4 V (as stated in the standards), the LVDS receiver circuit is typically designed to be robust against gate oxide breakdown even if the circuit is in a power saver mode while being present on an active data bus.
FIG. 1 shows a schematic circuit diagram illustrating a conventional self-biased folded cascode differential amplifier 100. Here, the differential amplifier 100 is being biased at a voltage level VDD/2, where VDD is the supply voltage, and VDD/2 is marked as voltage BIAS in FIG. 1. The amplifier 100 includes a biasing sub-circuit 110, which includes n-channel metal-oxide semiconductor (NMOS) transistors NB1, NB2, NB3, NB4, p-channel metal-oxide semiconductor (PMOS) transistors PB1, PB2, PB3, PB4, resistances RB1 and RB2, and output nodes VOP (for non-inverted output) and VOM (for inverted output).
In addition to the bias sub-circuit 110, the conventional cascode amplifier 100 has two sections 130, 120 configured for high and low common mode voltages respectively. Differential input voltages of the circuit, VINP and VINM (where VINP includes the non-inverted input and VINM comprises the inverted input), are applied to each of the sections 130, 120.
The section 120 catering to low common mode voltages includes transistors P1, P2 and PBIAS, and the ‘drain’ terminals of transistors P1 and P2 are coupled to nodes Y1 and Y2 of the bias sub-circuit 110 respectively. The section 120 is “alive” (i.e. active) at low common mode voltages, and pumps the input-dependent current to the bias sub-circuit 110 for amplification at outputs nodes VOP and VOM. However, the section 120 is “dead” (i.e. inactive) at high common mode voltages.
Similarly, the section 130 catering to high common mode voltages includes transistors N1, N2 and NBIAS and the ‘drain’ terminals of transistors N1 and N2 are coupled to nodes X1 and X2 of the bias sub-circuit 110 respectively. This section 130 is “alive” (i.e. active) at high common mode voltages, and pumps the input-dependent current to the bias sub-circuit 110 for amplification at outputs nodes VOP and VOM. However, the section 130 is “dead” (i.e. inactive) at low common mode voltages.
The conventional cascode amplifier 100 of FIG. 1 is operable for the entire common mode voltage range, provided that the transistors used are not stressed at higher supply voltages. However, if the maximum stress limit of the transistors is 2.0V, the circuit may be stressed when the amplifier 100 is used to design a 2.5V and/or 3.3V differential LVDS receiver using only thin-oxide 1.8V transistors (capable of handling a maximum of only 2.0V across any two nodes of the transistors). In such circumstances, the supply voltage level VDD is 2.5V or 3.3V, which is at a voltage level higher than the stress limit of 2.0V.
For example, for a low input common mode voltage, while the section 120 including transistors P1, P2 and PBIAS is “alive” when the input common mode voltage is towards ground, transistors N1 and N2 are in the OFF state (“dead”) and the voltage level at node VN typically drops down to ground. Since nodes X1 and X2 are at a higher voltage level at that point, transistors N1 and N2 may get stressed, as the voltage across different terminals of the transistors N1, N2, e.g. between drain and source (VDS), between gate and drain (VGD), or between drain and bulk (VDB), may exceed the permissible limits. This stress on transistors N1 and N2 can lead to a transistor breakdown eventually.
Similarly, for a high input common mode voltage, while the section 130 including transistors N1, N2 and NBIAS is “alive” when the input common mode voltage is towards the supply voltage, transistors P1 and P2 are in the OFF state (“dead”) and node VP is typically pulled up to supply voltage level. Since nodes Y1 and Y2 are at a lower voltage, transistors P1 and P2 may get stressed as the voltages, e.g. VDS, VGD, VDB may exceed the permissible limits. This stress on P1 and P2 may lead to a transistor breakdown eventually.
Also, when the amplifier 100 is in power saver mode or disable mode, while being present on the active data bus, which is transferring the data at voltages higher than 2.0V, the transistors N1 and N2 get stressed as the voltages between gate and source terminals (VGS) and between the gate and bulk terminals (VGB) may exceed 2.0V.